As Senior ASIC engineer you will:
- work on projects for the biggest players in ASIC world,
- design and verify digital circuits using VHDL/SystemVerilog languages (in verification we use the most modern verification methodology – UVM),
- drive project activities and guide junior engineers,
- create project documentation for designs certifications,
- work on a structured and well planned projects (in our projects we use Requirements Driven Development Processes).
- Bachelor or Master degree in computer science, electronics or related fields,
- 6+ years of experience in field of design or verification of ASIC/FPGA,
- very good knowledge of English,
- ability and lead project activities,
- valid work permit for Poland/European Union.
What we offer:
- very competitive salary package adequate to competencies,
- full employment contract or B2B contract,
- work on challenging projects.