Junior ASIC/FPGA engineer

As Junior ASIC engineer you will:

  • work on projects for biggest players in ASIC world,
  • design and verify digital circuits using VHDL and SystemVerilog language (in verification we use the most modern verification methodology – UVM),
  • create project documentation for designs certifications,
  • work on a structured and well planned projects (in our projects we use Requirements Driven Development Processes).

Our requirements:

  • Bachelor or Master degree in computer science, electronics or related fields,
  • very good knowledge of English,
  • very good understanding of Digital Design principles,
  • knowledge of at least one hardware description language (VHDL or Verilog/SystemVerilog),
  • good knowledge of Object Oriented Programming,
  • ability and willingness to learn and work as part of a team,
  • valid work permit for Poland/European Union.

Nice to have:

  • knowledge of communication interfaces such as I2C, SPI,
  • understanding of configuration management and change management principles,
  • basics of scripting languages,
  • experience with modern simulation tools (Modelsim/Questa, Simvision)

What we offer:

  • Competitive salary package adequate to competencies,
  • full employment contract,
  • work on challenging projects,
  • support of senior engineers to allow you quickly gain technical experience,
  • ability to smoothly go through career path steps.